Power systems may have several parallel connected converters having their respective single control loops operating in either voltage regulation or current limiting mode. Performance limitations have been discovered through system simulations. Non-uniform current sharing occurs despite voltage droop characteristics that facilitate near-uniform current-distribution. Due to random mismatches in component values, uneven current sharing among parallel connected converters exists. This causes system performance characteristics to exhibit large variations and system current sharing is found to be far from uniform, resulting in poor system performance and reliability.
Each power stage may include a DC to DC converter and a respective control circuit. Multiple current mode DC to DC converters may be connected in parallel to meet increased current demands of a load. With increased current demand, additional converters can be added as needed. When connecting multiple current mode converters to a common load, a significant problem is the unequal delivery of current by all of the converters. Each converter should operate independently yet contribute an equal amount of current to the load in the presence of different voltage references and component values.
A parallel connected DC to DC converter system may use a random current sharing approach in which many basic power converter stages are connected in parallel. It is desirable that many power systems of the same design have consistent steady state and transient responses as well as small signal characteristics of the paralleled converter system under resistive load conditions over dynamic operating conditions. Different systems have varying performance limitations such as inconsistent current limiting and sharing performance, poor voltage regulation, and poor output impedance characteristics. These systems have undesirable current sharing control as a primary cause of the performance limitations. These performance limitations lead to low reliability of power components under uneven current stresses, poor output transient responses, and large variances in output impedance. Various current sharing approaches have been developed to solve these disadvantages. These current sharing approaches are intended for uses in classes of power converters that usually do not exploit current-mode controls as the inner-most basic control loop. Current-mode controlled converters become desirable when using simple current sharing control. Non-current-mode controlled paralleled converter systems also have many limitations including non-uniform current sharing, large variances in system output impedance, degraded output voltage regulation, and inferior transient output performance.
The parallel connected converter system with random current sharing may include several power stages, for example, twelve power stages, connected in parallel at respective inputs and outputs. Each power stage consists of a converter with an associated power switch driving circuit and a control circuit. The control circuit produces a rectangular pulse width modulated signal driving power switching devices in the converter through the power switch driving circuit. When each power stage is operated as a stand-alone converter, the output voltage and current are fed back to the control circuit to regulate either the converter output voltage or the output current. Depending on load conditions, only a single feedback control loop is operating at any time in either voltage regulation or current limiting mode. As an example, each power stage is a single-ended step-up forward converter and boosts the input DC voltage, e.g. 28V +/-2V, to an output voltage, e.g., 123V +/-2 V with a nominal output power up to 210 W.
In this exemplar case, a converter power stage has voltage regulation and a current limiting control loop. Each power stage has two control modes of operation. The first mode is voltage regulation and the second mode is current limiting. In the output voltage regulation mode, the output voltage is regulated and stabilized to 123V +/-2 V with linear droop characteristics from 125V to 121V corresponding to the load condition from zero to 1.75 A. When the load current is just above its nominal level, e.g. 1.75 A, the power stage operation starts shifting to a current limiting mode in which the output voltage begins to decrease below 121V with a moderate regulation error. When the load demands more current, the current limiting operation becomes fully active by regulating the load current about 10% above its nominal value with 1.96 A set as the output short-circuit current.
Different power stages are not likely to be the same. The power stages will operate in different modes with some of the power stages operating in the voltage regulation mode and others in the current limiting mode, primarily because of differing component values and independent reference voltages. Additionally, some of the power stages operating in voltage regulation mode may operate in the continuous conduction mode while other power stages operate in the discontinuous conduction mode. Power stages operate in the discontinuous conduction mode when the output current drops below 0.33 A. When a converter power stage operates in the discontinuous conduction mode, the converter power stage exhibits different large and small signal characteristics as compared to those obtained from the same converter operating in the continuous conduction mode. Hence, a conventional continuous conduction mode power stage model may not be suitable for design verification through simulation of light load or mismatched conditions that may have some power stages operating in the discontinuous conduction mode while other power stages operate in the continuous conduction mode. A high-fidelity large signal model of the power stage can be developed to determine the mode of operation in the discontinuous conduction mode or continuous conduction mode for both large and small signal analyses. Under variations of load and component tolerances, this large signal model allows more accurate and realistic performance simulations of dynamic operations as a function of output impedances, loop gain frequency responses of the converters operating in voltage regulation or current limiting mode, and step load responses.
For simplicity of discussion, the model of paralleled converter system may be partitioned into two groups of paralleled power stages. In the model, an ideal voltage source supplies power to all the converters that transfer most of the power through an output cable to a resistive load. When N power stages are operating identically in either voltage regulation or current limiting mode, a lumped model of N paralleled power stages is used to share the same feedback control circuit. The large signal model of N paralleled power stages is simply derived from the basic power stage by proper scaling of power component values, that is, power inductance scaled by 1/N, filter capacitance scaled by N, and parasitic series switching loss scaled by 1/N. The remainder of the power stages operating identically but in a different mode from the former group will be likewise scaled by the total number of converter minus N instead of N. Electronic circuit computer simulations can be performed to evaluate the basic transient and dynamic performance, that is, the stability of the voltage regulation and the current limiting loop gains, the output impedance, and the step load and fault transient responses. The converter system model includes several power stages operating in either voltage regulation or current limit mode depending on the load condition and the reference voltage. The two groups of power stages are set to be either identical or within 1% mismatch of their reference voltages. Despite the reference voltage mismatches, all twelve power stages operate in the voltage regulation mode under a 1 A load or other light to moderate load conditions. The simulation results may reveal many limitations of the converter system in both the current sharing performance and other dynamic performance characteristics, such as output impedance, voltage regulation, and current limiting loop gains.
From system to system, the paralleled power stages exhibit an inconsistent current sharing and current limiting performance. Small signal characteristics of current limiting loop gain reveal significant variations in unity gain frequencies under different load conditions. The current limiting responses obtained from non-identical power stages and control circuit due to slight component mismatches are compared to one another. These sets of responses show significant differences in terms of control bandwidths and imbalances in the currents distributed among the power stages in both transient and steady state values of the current limiting level. Due to the randomness in current sharing, the transient response during step loads can cause one or more power stages to always exceed or reach current limiting operation while the remainder never experience such stresses. Consequently, utilization time distributed among the paralleled power stages is far from uniform, and the system reliability is degraded. The power stages that suffer from high output current transient stresses will degrade at a faster rate than those not experiencing excessive stresses.
The power stages exhibit low DC gain and a slow voltage regulation loop response. To help achieve steady state near-uniform current sharing among the power stages, the voltage regulation control loops for respective power stages must provide at least near identical droop characteristics. The DC gain of the voltage regulation loop is then limited to a moderate value, e.g., less than 30 dB, to facilitate non-stiff characteristics of the output voltage. Consequently, the bandwidth of the control loop is restricted to low frequencies due to basic roll-off characteristics of the output filter in each power stage. The low control bandwidth also results in a slow transient performance as compared to that of a single converter system in which the voltage loop gain bandwidth can be extended due to the absence of current sharing complications.
The paralleled power stages exhibit a significant variation of the output impedance. There are many combinations of operational modes caused by random mismatches among the twelve power stages. As system to system performance inconsistency is apparent, the output impedance characteristics of such converter systems of the same design can be far different even at the same line and load condition. Significant variations of output impedance characteristics are realized when operating the power stages in various modes, including voltage regulation, current limiting, discontinuous conduction and continuous conduction modes. Under existing control approaches, there is no sure way to control the mismatches in component values for the reduction of the output impedance variances. This can result in an overlap between the system output and load impedances and contribute to a high risk of oscillation on output voltage and current sharing among power stages.
The random current sharing without shared-bus arrangement have several disadvantages. Non-uniform current sharing is due to mismatches in component values leading to different modes of operation existing among paralleled converters. The output voltage regulation performance, both in steady state and transient condition, is degraded to compromise with tolerable current sharing that is not always near-uniform. Large variations in output impedance is due to slight circuit and control mismatches among paralleled converters, leading to inconsistent output impedance characteristics from system to system. Inconsistent current sharing performance is realized from system to system due to inconsistent mismatches in component values and/or reference voltages within paralleled converters. Undesirable interactions among parallel connected converters lead to complicated stability designs due to different modes of operation among paralleled converters, each of which is controlled differently under respective dedicated voltage regulation control loops. The lack of an accessible common control port prohibits uniform control to the paralleled converters to meet other control objectives such as system over-voltage protection.
A shared-bus arrangement has been disclosed in U.S. Pat. No. 5,157,269 in which the shared-bus is formed by wired-OR ideal rectifiers with a pull down resistor to a ground reference. The wired-OR ideal rectifiers provide a mean to output the maximum sensed current signal selected from all sensed current signals being proportional to the respective currents through the respective converters. The rectifiers have to be ideal because the signals being sensed must be proportional to the actual power stage currents. Zero voltage drop across the rectifiers is required to gain accuracy of the shared-bus signal that is used as a master current reference signal for uniform current sharing control of the slave converters. In this approach, the output currents of the slave converters are less than the output currents of the master converters. The master converters are not controlled in the same direction as are the slave converters. This sharedbus approach is for controlling the parallel connected converters that do not necessarily have current-mode operation in the inner most control loops. The approach serves as a mean to produce different reference voltages to which the output voltages of the respective converters are individually regulated as a way to equalize the output currents of the converters. Each converter has a respective voltage regulation feedback control path that generates different control signal strength and/or direction compared to the other converters. Due to many feedback paths of voltage regulation control loops having different reference voltages, conflicts are created in voltage regulation control. During any transient due to step load or step line conditions, the master and slave operation can be exchanged many times because the output current of a master converter is dependent on the output currents of the slave converters by sharing the same output load circuit. This dependency introduces oscillation of current sharing during transients, resulting in indefinite exchanges in master and slave operations. These and other disadvantages are solved or reduced using the present invention.